Asynchronous Register Less NULL Convention Logic (RL-NCL) Pipeline Architectures Using Basic Gates

Gabriel C. Duarte; Duarte L. Oliveira

doi:10.36561/ING.23.7

Autores/as

Gabriel C. Duarte Aeronautical Technological Institute, Brasil https://orcid.org/0000-0002-6739-8709
Duarte L. Oliveira Aeronautical Technological Institute https://orcid.org/0000-0002-9704-6616

DOI:

https://doi.org/10.36561/ING.23.7

Palabras clave:

Circuitos Asíncronos, NCL, RL-NCL, FPGA, Pipeline

Resumen

Los circuitos asíncronos son una alternativa para el diseño de sistemas digitales que se está convirtiendo en el interés de muchos investigadores en el área del diseño digital debido principalmente a su bajo consumo y robustez. Uno de los paradigmas de diseño más convincentes de los circuitos asíncronos es la NULL Convention Logic (NCL). La pipeline es una técnica muy común utilizada en circuitos digitales para lograr un alto rendimiento. Aunque se puede implementar una pipeline utilizando puertas NCL, trabajos recientes han demostrado que las pipelines sin registro son posibles utilizando puertas NCL modificadas. En este artículo, propusimos dos nuevas arquitecturas de pipeline Register-Less NCL (RL-NCL) y un paradigma de diseño, que pueden implementarse incluso en Field Programmable Gate Arrays (FPGA) o utilizando el método de celdas estándar. El nuevo diseño de la arquitectura propuesta logró una reducción media del área del 27,32%, una reducción media de la latencia del 14,1% y un aumento medio del rendimiento del 5,54% en comparación con la arquitectura de pipeline NCL convencional.

Descargas

Los datos de descargas todavía no están disponibles.

Citas

G. C. Duarte and D. L. Oliveira, “A novel asynchronous pipeline architecture with less-registers using null convention logic,” in 2021 IEEE URUCON, 2021, pp. 36–41.

B. H. Calhoun, Y. Cao, X. Li, K. Mai, L. T. Pileggi, R. A. Rutenbar, and K. L. Shepard, “Digital circuit design challenges and opportunities in the era of nanoscale cmos,” Proceedings of the IEEE, vol. 96, no. 2, pp. 343–365, 2008.

L. Ye, Z. Wang, Y. Liu, P. Chen, H. Li, H. Zhang, M. Wu, W. He, L. Shen, Y. Zhang, Z. Tan, Y. Wang, and R. Huang, “The challenges and emerging technologies for low-power artificial intelligence iot systems,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 68, no. 12, pp. 4821–4834, 2021.

T. Le Thanh, L. T. Tri, and H. Trang, “Power consumption improvements in aes decryption based on null convention logic,” International Journal of Circuits, Systems and Signal Processing, vol. 15, pp. 254–264, 2021.

S. M. Nowick and M. Singh, “High-performance asynchronous pipelines: An overview,” Ieee design & test of computers, vol. 28, no. 5, pp. 8–22, 2011.

K. M. Fant and S. A. Brandt, “Null convention logic/sup tm/: a complete and consistent logic for asynchronous digital circuit synthesis,” in Proceedings of International Conference on Application Specific Systems, Architectures and Processors: ASAP ’96, 1996, pp. 261–273.

S. Smith and J. Di, Designing Asynchronous Circuits using NULL Convention Logic (NCL), 2009.

M. Chang, P. Yang, and Z. Pan, “Register-less null convention logic,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 64, no. 3, pp. 314–318, 2017.

L. Zhou, R. Parameswaran, F. A. Parsan, S. C. Smith, and J. Di, “Multi-threshold null convention logic (mtncl): An ultra-low power asynchronous circuit design methodology,” Journal of Low Power Electronics and Applications, vol. 5, no. 2, pp. 81–100, 2015.

S. Mutoh, T. Douseki, Y. Matsuya, T. Aoki, S. Shigematsu, and J. Yamada, “1-v power supply high-speed digital circuit technology with multithreshold-voltage cmos,” IEEE Journal of SolidState Circuits, vol. 30, no. 8, pp. 847–854, 1995.

A. D. Bailey, J. Di, S. C. Smith, and H. A. Mantooth, “Ultra-low power delay-insensitive circuit design,” in 2008 51st Midwest Symposium on Circuits and Systems, 2008, pp. 503–506.

J. Sparso and S. Furber, Principles of Asynchronous Circuit Design - A Systems Perspective, 1st ed. Springer, 2001.

D. Khodosevych and A. A. Sakib, “Evolution of null convention logic based asynchronous paradigm: An overview and outlook,” IEEE Access, vol. 10, pp. 78650–78666, 2022.

V. Satagopan, B. Bhaskaran, W. K. Al-Assadi, S. C. Smith, and S. Kakarla, “Dft techniques and automation for asynchronous null conventional logic circuits,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 15, no. 10, pp. 1155–1159, 2007.

F. A. Parsan and S. C. Smith, “Cmos implementation comparison of ncl gates,” in 2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS), 2012, pp. 394–

D. L. Oliveira, O. Verducci, L. A. Faria, and T. Curtinhas, “A novel null convention logic (ncl) gates architecture based on basic gates,” in 2017 IEEE XXIV International Conference on Electronics, Electrical Engineering and Computing (INTERCON), 2017, pp. 1–4.

D. L. Oliveira, O. Verducci, V. L. V. Torres, R. Moreno, and L. A. Faria, “Synthesis of QDI Combinational Circuits using Null Convention Logic Based on Basic Gates,” Advances in Science, Technology and Engineering Systems Journal, vol. 3, no. 4, pp. 308–317, 2018.

S. M. Nowick, “Automatic synthesis of burst-mode asynchronous controllers,” Stanford, CA, USA, Tech. Rep., 1995.

S. Yang, “Logic synthesis and optimization benchmarks user guide: Version 3.0,” MCNC Technical Report, Tech. Rep., Jan. 1991.